The present invention relates generally to reducing jitter in a phase locked loop (PLL), and more particularly to methods and apparatus for reducing jitter using two reference frequency doublers, two equalizers, and a phase detector.
A conventional phase locked loop (PLL) typically includes a frequency phase detector which receives a reference signal, a filter, a voltage-controlled oscillator (VCO), and a divider circuit. If the reference signal received by the frequency phase detector has a relatively low frequency, a large feedback divider ratio is required by the PLL. A large feedback divider ratio requires that the divider circuit have a relatively large number of dividers, which undesirably introduces phase xe2x80x9cjitterxe2x80x9d into the signals. Jitter is an adverse signal effect which can lead to noise and even logic errors at higher communication speeds. The large feedback divider ratio also means that the loop gain of the PLL will be lower for a given supply voltage, which makes the gain distribution for noise less ideal and also increases jitter.
One solution to this problem is to increase the frequency of the reference signal received by the frequency phase detector. However, conventional XOR-based frequency doublers typically distort the duty cycle of reference signals due to integrated circuit (IC) process variations. This distortion may be severe enough to render the approach ineffective.
This invention provides an improved phase-locked loop (PLL) circuit. In accordance with one embodiment of the invention, a PLL circuit includes a reference signal generator having an input, a frequency quadrupler, an equalizer, and an output. The PLL circuit further includes a filter having an output coupled with an input of a voltage-controlled oscillator (VCO), a first divider having an input coupled with an output of the VCO, and a frequency phase detector having a first input coupled to an output of the first divider and a second input coupled to the reference signal generator output. The PLL circuit further includes a second divider having an input coupled with the output of the VCO, and a phase detector having a first input coupled to an output of the second divider and a second input coupled to the reference signal generator output. The PLL circuit further includes a multiplexer having a first input coupled to an output of the frequency phase detector, a second input coupled to an output of the phase detector, and an output coupled to an input of the filter.
According to another embodiment of the invention, a PLL circuit configured for reduced jitter includes a reference signal generator configured to quadruple a frequency of a first reference signal to produce a second reference signal, and a filter coupled in series with a voltage controlled oscillator (VCO). The PLL circuit further includes a frequency phase detector configured to generate a first error signal based on a frequency difference between the second reference signal and a first divided VCO output signal, and a phase detector configured to generate a second error signal based on a phase difference between the second reference signal and a second divided VCO output signal at each rising and falling transition of the second reference signal. The PLL circuit further includes a multiplexer configured for initially receiving the first error signal until the frequencies of the first divided VCO output signal feedback signal and the second reference signal match, and thereafter for receiving the second error signal, and to provide the first or second error signal to the filter.